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Library Catalogue

Logic design and verification using systemVerilog (revised) (Record no. 5225)

MARC details
000 -LEADER
fixed length control field 02323nam a22001937a 4500
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20250108142639.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field 250108b |||||||| |||| 00| 0 eng d
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9781523364022
040 ## - CATALOGING SOURCE
Transcribing agency National Institute of Technology Goa
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.395
Item number THO/LOG
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Thomas, Donald
245 ## - TITLE STATEMENT
Title Logic design and verification using systemVerilog (revised)
250 ## - EDITION STATEMENT
Edition statement 1st
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Place of publication, distribution, etc. USA:
Name of publisher, distributor, etc. CreateSpace Independent Publishing,
Date of publication, distribution, etc. 2016
300 ## - PHYSICAL DESCRIPTION
Extent xxii, 314p.: 15x20x1; Paperback
520 ## - SUMMARY, ETC.
Summary, etc. About the book: SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs. The majority of the book assumes a basic background in logic design and software programming concepts. It is directed at: -students currently in an introductory logic design course that also teaches SystemVerilog, -designers who want to update their skills from Verilog or VHDL, and -students in VLSI design and advanced logic design courses that include verification as well as design topics. The book starts with a tutorial introduction on hardware description languages and simulation. It proceeds to the register-transfer design topics of combinational and finite state machine (FSM) design - these mirror the topics of introductory logic design courses. The book covers the design of FSM-datapath designs and their interfaces, including SystemVerilog interfaces. Then it covers the more advanced topics of writing testbenches including using assertions and functional coverage. A comprehensive index provides easy access to the book's topics.The goal of the book is to introduce the broad spectrum of features in the language in a way that complements introductory and advanced logic design and verification courses, and then provides a basis for further learning.Solutions to problems at the end of chapters, and text copies of the SystemVerilog examples are available from the author as described in the Preface.
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Source of heading or term Electronic and Communication Engineering;
Topical term or geographic name entry element Electronic and Communication Engineering; Combinational logic; Finite state machines; Hardware threads; Testbenches; Simulation Kernel; FPGA
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme Dewey Decimal Classification
Koha item type Books
Suppress in OPAC No
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Home library Current library Shelving location Date acquired Source of acquisition Cost, normal purchase price Total checkouts Full call number Barcode Date last seen Price effective from Koha item type Public note Date last checked out
    Dewey Decimal Classification     Central Library NIT Goa Central Library NIT Goa General stacks 08/01/2025 T V Enterprises, Mumbai 6064.66   621.395 THO/LOG 11126 08/01/2025 08/01/2025 Reference Reference Book Rack number 39(A) & (B)  
    Dewey Decimal Classification     Central Library NIT Goa Central Library NIT Goa General stacks 08/01/2025 T V Enterprises, Mumbai 6064.66 1 621.395 THO/LOG 11127 29/01/2025 08/01/2025 Books Book Rack number 20(B) 14/01/2025
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